Implementation Of Blocks Using Mentor Graphics Computer Science
Logic gates are generally constructed using transistors depending on the technologies. The new technology which used is CMOS technology where MOSFET transistors are used for constructing integrated circuits. CMOS stands for complementary metal oxide semiconductor. Every logic gate is complementary because every gate structure is made up of pull up network where p type transistors are used and pull down network where n type transistors are used. These two networks are complementary to each other.
Figure () shown is symbol of n-channel MOSFET. Each transistor consists of four terminals, gate, source, base and drain. The gate is a metallic layer deposited on the substrate (body) and voltage is applied across the gate to control the flow of current between drain and source.
If the gate voltage (Vgs) is zero, there is no current flow from drain to source because there is no path between drain and source, the MOSFET is OFF i.e., cut off. If the gate voltage (Vgs) is positive and more than the threshold value, then current flows from drain to source because there is a channel between drain and source. In this case, the MOSFET is ON (saturation).
Figure () shown is the symbol of p-channel MOSFET. The operation of p channel is similar to n type but Vds and Vgs are negative. When the gate voltage is negative i.e., zero less than the threshold voltage, there exists the channel between drain and source allows current to flow from source to drain. The transistor is ON i.e., saturation region. If the gate voltage is positive then the transistor turns OFF.
() n-channel MOSFET () p-channel MOSFET
CMOS logic uses both n channel and p- channel MOSFET to perform logic functions. CMOS technology has an advantage of low power dissipation compared to TTL logic. CMOS circuit s consists of pull up network and pull down network where pull up network consists of PMOS transistors and pull down network consists of NMOS transistors. Figure below shown is CMOS inverter.
When the positive voltage (logic 1) is applied to the gate inputs, transistor Q1 is OFF and transistor Q2 is ON and this makes the transistor Q2 to connect to VSS giving zero output. FIGURE (C): CMOS inverter
When the zero volts is applied to the input, transistor Q1 is on and transistor q2 is off and this condition makes the transistor Q1 to connect to VDD (supply voltage) giving out high output.CMOS AND Gate:
Figure () shown is CMOS two input AND gate. Input A and input B are the two inputs to gate and output is the output of the AND gate. In the CMOS 2 input AND gate, number of transistors used in the circuit are 6(3 PMOS transistors and 3 NMOS transistors). C35B3CO technology is used to build this circuit and the characteristics of PMOS and NMOS are described above. The PMOS transistor Q1 and Q2 are connected in parallel i.e., drain of the transistor Q1 is connected to the drain of the transistor Q2 and this section forms pull up network .The NMOS transistors are connected in series i.e., source of the transistor Q3 is connected to the drain of the transistor Q4 and this forms pull down network. The parallel connection of the PMOS transistors are connected to the series connection of the NMOS transistors and output at this point is CMOS NAND gate and this is connected to the CMOS inverter circuit to form CMOS or gate.
C:UsersVardanDesktopAND gate picturesand gate.png
Implementation of the CMOS two input AND gate using mentor graphics is shown in page ().The output waveforms for the CMOS two input AND gate is as shown in the page ().
The design is checked for errors and then it is net listed and simulated. Characteristics of the input signals given are shown below.
Name: in1, signal: inA
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