Reducing Power Dissipation In BIST Computer Science

Essay add: 29-03-2016, 19:03   /   Views: 18

This paper presents a new approach to reduce power consumption during testing of a chip in the scan based output of built in self test (BIST) architecture. . In the proposed approach an algorithm is developed to restructure the output sequence so that the transitions in the output sequence are optimized to minimize the power consumption for a given input sequence. Experimental results show that the power dissipation of the architecture with the proposed technique reduces significantly compared to the other existing techniques and requires less hardware.

Keywords- BIST switching activity, random pattern and power dissipation.


Heat dissipation in ICs, when in operation, is a major problem as it may overheat and damage or even destroy the ICs. The amount of heat dissipated is proportional to the power consumed by the chips. The heat dissipation during test is higher than during normal mode [1]. If heat dissipation during test is not controlled, expensive methods like special cooling mechanisms on the test floor or bigger packages to dissipate the extra heat might be required. Hence there is a need for cost effective methods to ensure that the heat dissipation during testing is kept at manageable level, Therefore now a days researcher more interested in low power BIST [4]. The advantage of low power BIST is to avoid the risk of damaging the Circuits under Test (CUT) and save the cost of expensive packages or external cooling devices for testing The amount of power consumed by a CMOS circuit is proportional to the switching activity in the chip [2]-[3]. Several techniques have been devoted to develop methodologies, technologic solutions and algorithms to reduce average power consumption [5] [6]. BIST power consumption mainly depends upon some factors such as clock, combinational and sequential logic. In the clock power reduction category, disabling or gating the clock of scan chains are proposed [7] [8]-[9], these technique effectively reduce the clock power consumption, which is shown to be a significant component of the test power [10]. Modifying the clock increases the risk of skew, and even sometime it cause serious failure in whole chip. In sequential circuit scan chain fix by reordering the bits that will minimize the toggle in scan chain shift [11]. The low transition Random test pattern generator (LT-RTPG) is proposed to reduce the number of toggles of the scan input patterns [13]. 3-weight weighted random technique is further proposed to reduce power but it taking more hardware [14]. Effective way to reduce combinational logic power is the toggle suppression technique, which holds the data Output of scan cells so the combinational circuits do not toggle when scan chains are shifting [15, 16] But this technique are not suitable for sequential circuits. Reordering concept is used in many BIST [17, 18] like SWR BIST reducing the power more than above technique, but it requires more hardware. In this paper a new algorithm is proposed for reducing the power dissipation in BIST.This algorithm reduce the number of transition of bit in BIST. Low bit (0) is passing first and high bit (1) passes later, so in this way it overall reducing the transition in BIST. The main advantage of this algorithm its taking less hardware as compare to other BIST .The experimental result on benchmark circuits shows full scan chain is restructure and it significantly reduce the power dissipation to 80% without taking any extra hardware.


The transition that occurs at scan input can propagate into internal circuit lines causing more transitions. Here we focus on minimizing the number of transitions caused only by test patterns that are scanned. Even though we focus on minimizing the number of transitions caused only by test patterns, our extensive experiments show that the proposed BIST can still reduce switching activity significantly. A transition at the input of the scan chain at scan shift cycle, which is caused by scanning in a value that is opposite to the value that was scanned in at the previous scan shift cycle, continuously causes transitions at scan inputs. since it is very difficult to generate test pattern by a random pattern generator that cause minimal number of transition while they are scanned into the scan chain, we are focusing on minimizing number of transition on caused only by test patterns that are scanned in. Fig.1 describes scanning a scan test pattern 010110 into a scan chain that has five scan flip-flops. Since a 0 is scanned into the scan chain first time, the 1 that is scanned into the scan chain second time causes a transition at the input of the scan chain and continuously causes transitions at the scan flip-flops it passes through until it arrives at its final destination. In contrast, the 1 that is scanned into the scan chain at the next cycle causes no transition at the input of the scan chain and arrives at its final destination at time without causing any transition at the scan flip-flops it passes. This shows that transitions that occur in the entire scan chain can be reduced by reducing transitions at the input of the scan chain. Since transitions at scan inputs propagate into internal circuit lines causing more transitions, reducing transitions at the input of scan chain can eventually reduce switching activity in the entire circuit.

Fig 1- Transition of bits from LFSR

Related previous work

In most BIST architecture LFSR is the input. LFSR generates random pattern, these random pattern transfers to scan chain, from scan chain all random patterns are transferred to circuit under test. Based on the mechanisms that are used to generate the deterministic patterns, logic BIST techniques can be classified into two categories: methods that generate deterministic patterns by controlling the states of the LFSR [19] [22], [23] and techniques that modify the patterns generated by the LFSR [20], [21], .LFSR reseeding is an example of a BIST technique that is based on controlling the LFSR state. LFSR reseeding can be static, i.e., the LFSR stops generating patterns while loading seeds, or dynamic, i.e., test generation and seed loading can proceed simultaneously. A set of linear equations is solved to obtain the seeds, and the test vectors are reordered to facilitate the solution of this set of linear equations. Width compression is combined with reseeding to reduce the hardware overhead. Bit-fixing and weighted random BIST are examples of techniques that rely on altering the patterns generated by the LFSR to embed deterministic test cubes. In [25], a hybrid BIST method based on weighted pseudorandom testing is presented. A weight of 0, 1 or (unbiased) is assigned to each scan chain in CUT. The weight sets are compressed and stored on the tester During test application, an on-chip look-up table is used to decompress the data from the tester and generate the weight sets. In order to reduce the hardware overhead, scan cells are carefully reordered and a special approach is used to generate suitable pattern to reduce switching activity.

Fig 2 - General structure of BIST with psuedorandom pattern


The algorithm is proposed to reorder the scan chain ,in this algorithm whatever the pattern that are coming from LFSR get reorder to reduce the switching activity .for example from figure 3 we can see the random pattern from LFSR 1 0 1 0, this pattern get reorder by applying minimum cost function logic ,first we are taking i & j bits , if we compare i & j , j is minimum then j get loaded into the scan chain , then the comparison in next two bits k & L , L is minimum , this get loaded into the scan chain , next whatever the bit left I & K , comparison on these two bits takes place , whatever minimum bit that get loaded into the chain , finally the scan chain get reordered in a decreasing order. Hence switching activity get reduces and finally the power get reduces.

Random pattern from LFSR

I j k l

1 0 1 0

3 times switching

For i = 1

For j = 0

A[i][j]=min-cost (i,j)=0

For k = 1

For l = 0

B[k] [l] = min cost (k, l) = 0

Finally C[i][k] = min cost (i,k) = 1

Fig 3 Reordered Scan Chain

proposed bist

In proposed BIST Architecture , the random pattern that are generating from LFSR giving to proposed algorithm , this algorithm reordering the random pattern & finally loading into the scan chain , from figure 4 , we can see that the random pattern that are generating from LFSR that are reordered in a scan chain , hence switching activity get reduces as comparison to previous bits , finally the power dissipation get reduces if we compare this BIST to other BIST architectures this BIST significantly reduces 80% of power . If we look This BIST area wise, within same area as normal BIST, it reducing the power, the algorithm we applied is not taking any extra hardware, within same hardware, it's giving the better results. Finally our enhancement is better as comparison to previous work.

Random patterns Re-ordered pattern

Fig4 -Architecture of Proposed BIST

experimental resultPower Dissipation

Experiment were done using a benchmark circuits .To accurately model the switching activities, logic simulations of CUTs in BIST mode are preformed in a bit-by-bit shifting way. Experiment was done using a power analysis tool (Mentor graphics IC station) calculates the average power. Table1 compares the experimental results of a regular pseudo random BIST versus the proposed BIST. The pseudo random BIST is implemented by feeding the scan chains by a 4 bit LFSR.In table 1 Columns under the heading LFSR give results of pseudo random BIST while columns under the heading proposed give results of proposed BIST. The proposed algorithm effectively reduces the power by 80%.With scan cell

reordering. Figure 5 shows the power dissipation on different benchmark circuits. The Proposed BIST is the lowest power technique (80% reduction).


Table 3 shows number of gates of the BIST and of the benchmark circuits. Columns under the heading LFSR give results of pseudo random BIST while columns under the heading proposed give results of proposed BIST. This number of gate is count by using synthesis report of xilinx tool. According to the result number of LUT and flip flop occupy by Pseudo random and Proposed BIST are same. This result is shown in fig 6 .Its clear from the result proposed BIST is not taking any extra hardware within same area it giving low power dissipation.


This paper presents a low hardware scan based proposed BIST that can reduce switching activity in CUT during BIST. Since the correlation between consecutive patterns applied to a circuit during BIST is significantly lower, switching activity in the circuit can be significantly higher during BIST than that during its normal operation. Excessive switching activity during test application can cause several problems. Experimental results for benchmark circuits in demonstrate that the Proposed BIST can significantly reduce switching activity during BIST without taking any extra hardware. The proposed BIST structure does not require modification of mission logic which can cause performance degradation.

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